1. Field of the Invention
The invention relates to an integrated semiconductor memory which is subdivided into a plurality of function units, having m leads addressable from the outside, internal signal lines leading from the function units to the leads, internal signal lines connecting the function units with one another, and a test unit recognizing a test mode from a code word applied to k (k.ltoreq.m) leads.
2. Description of the Related Art
Block circuit diagrams of various semiconductor memories are shown in the journal Mikroelektronik [Microelectronics], Vol. 4 (1990), No. 1, pp. 12-31, and more specifically pages 13/15 discuss video RAMs; pages 18/20 discuss SRAMs; and page 28 discusses DRAMs. As can be seen therein, the semiconductor memory is divided into several function blocks, such as cell fields, bit-word line decoders, clock generators, and so forth. Each of the function blocks can be further subdivided into smaller units. In large-scale integrated semiconductor memories, test units are usually provided as well, which are intended to permit effective, rapid testing of the memory cells.
In the course of large-scale integration of semiconductor memories, it is not only the memory capacity but also the number and complexity of peripheral function units that increase. For instance, a selection can be made between various forms of organization and modes of operation of the semiconductor memory. For each new operating mode, the entire memory, in other words all of its memory cells, must sometimes be tested. Purposeful testing of an individual function unit is impossible in current semiconductor memories. If an individual function unit is not functioning perfectly or if it is completely defective, conclusions must be drawn, for instance by suitable interpretation, as to which function unit is defective, by testing the memory cells. Often that can only be done with difficulty, or an incorrect conclusion is drawn. In the development phase of a semiconductor memory as well, it would be highly advantageous to test targeted individual function units, in order to shorten the development times. Finally, the testing and analysis time for a semiconductor memory can be considerably shortened if the most important function units of the semiconductor memory are tested first, and then the interaction of the function units is checked in usually simpler tests.